1. Field of the Invention
The present invention relates to a pixel structure, and more particularly, to a pixel structure having a constant gate-drain parasitic capacitance.
2. Description of the Prior Art
Conventional TFT-LCD (thin film transistor liquid crystal display) includes a TFT array substrate, a counter substrate and a liquid crystal layer sandwiched in-between. The TFT array substrate includes a plurality of scan lines, a plurality of data lines, a plurality of TFTs disposed between the scan lines and the data lines and a pixel electrode disposed corresponding to each TFT. The counter substrate includes a common electrode. Each aforementioned TFT includes a gate electrode, a semiconductor layer, a source electrode and a drain electrode, and functions as a switching element of a liquid crystal unit.
The manufacturing process of the TFT array substrate usually includes a plurality of exposure, photolithography and etching processes. In general manufacturing technology, the gate electrode and the scan line are formed by a first metal layer, and the source electrode, the drain electrode and the data line are formed by a second metal layer. At least an inter-layer dielectric (ILD) layer is disposed between the first metal layer and the second metal layer. In the TFT structure, the gate electrode at least partially overlaps the drain electrode; therefore, the so-called gate-drain parasitic capacitance (Cgd) exists due to the overlapping of the gate electrode and the drain electrode.
With regard to the LCD, a voltage transferred from the data line is applied to a liquid crystal capacitor Clc formed by the pixel electrode, the common electrode and the liquid crystal layer; and the voltage has a specific relation to a transmittance of liquid crystal molecules in the liquid crystal layer. The voltage applied to the liquid crystal capacitor Clc depends on grayscale values of an image displayed. However, due to the existence of the gate-drain parasitic capacitance, the voltage difference on the liquid crystal capacitor Clc will vary when the signal on the gate line varies. The voltage change is known as the feed-through voltage ΔVp, and can be represented by an equation below.ΔVp=[Cgd/(Clc+Cgd+Cst)](Vgon−Vgoff)
Where Vgon−Vgoff represents an amplitude of a voltage pulse applied on the scan line, and Cst stands for a storage capacitor.
During the TFT manufacturing process, a misalignment by the machine movement may cause the TFT components to deviate from their designated positions. Especially, an overlapping area of the gate electrode and the drain electrode varies, therefore, the gate-drain parasitic capacitance Cgd varies as well and different pixels have different feed-through voltages ΔVp. A problem of display picture quality degradation is generated during displaying; therefore, an objective for the TFTs to keep the gate-drain parasitic capacitances (Cgd) stable is desired.